1. Field
This disclosure relates generally to semiconductor manufacturing and processing, and more specifically, to methods for fabricating highly reliable interconnects.
2. Related Art
Problems in the art include, for example, premature via failures due to tungsten plug corrosion that is not otherwise detectable through in-line, end of line, or final test screening. Problems in the art further include yield decrease due to localized charging that can occur at an inter-layer dielectric (ILD) polish portion of a semiconductor device manufacturing process. Furthermore, prior known processing techniques do not address tungsten corrosion or localized charging resulting from chemical mechanical polishing (CMP) processing.
Accordingly, there is a need for an improved method for overcoming problems in the art as discussed above.